Monday, May 9, 2011

Xilinx DDR SDRAM interface, generated by EDK 10.1

I have got NGR (my ISE 10.1.sp3 does support mem core gen for unknown reason)

I do not see it among the Xilinx Memory Interface App Notes and looks like a plb_ddr. Is it better? Why commands are generated in sync with sys_clk? What is the length of internal feedbacks?

The FB seems to be in phase with CLK0 at SDRAM. Why its 90° shifted version is used for clocking the receiving part? Since it does not account for the backward trace length from SDRAM to FPGA but CLK and strobes must be in phase, wouldn't it be better to use one of the strobes for clocking?

PS. I have done calibration measurements on XUPv2P. It seems that this board and PLB_DDR controller were designed for each other. The clock seems to be delayed 180° on the board, so that controller needs not clock SDRAM commands anti-phasely to SDRAM clocking. But, separating SDRAM clock from cmd/addr/wr_data and rd_data (two extra DCMs) allows to adjust the phase for read and write.

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