Saturday, August 6, 2011

Hiding refresh latency

I have a PC3200: 200MHz DDR (400 mln transfers/sec) 64-bit DIMM consisting of 2 ranks * 4 banks/rank * 2^13 rows/bank * 2^10 col/row. We can switch rows in banks while keeping data bus busy with read. Refresh is required every 7.8 us or 62.4 (ca 12k cycles) us if you do a burst refresh to refresh the whole memory in 64 ms. One row refresh takes 14 clock cycles. We cannot hide this refresh latency the same way as we hide row switching - read must be stopped during every row refresh.

Yet, I/O access to a row refreshes it naturally. So, if we traverse all the memory, as I do, we may access only a limited number of columns, n, per row and switch to another row. We need to iterate 2 ranks * 4 banks/rank * 2^13 rows/bank = 64k rows in 62.4 ms. This means that 64k rows * n cycles/row * 1/200M sec/cycle < 62.4 ms or n < 200 cycles/row. This is 400 col/row -- almost a half of 1k in memory traverse in 62.5 ms.

There is one problem, though: consumer must not stall the controller otherwise, auto refresh must be used and this scheme makes no sense.

No comments: