Saturday, October 12, 2013

Functions, synthesis and static structure

In addition hierarchical structural discription, which is already a hardware, VHDL allows procedural description to describe function of basic components. These need to be synthesized if you want to implement them in hardware. Basically, synthesis maps the programming-language described processes into elementary, pre-defined block. You can see the resulting structure in the RTL Viewer.

I always considered the synthesis as extracting the logic(al functions) of the procedural process. These may be purely combinatorial or reg-excitating functions. This is true. But after getting familiar with, I see that functions are static. The (logical) functions are single-assignment creatures. They are static entities. What synthesis does it the extraction of these static functions.

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